1. Field of the Invention
The invention relates to electronic communication, particularly to signaling protocol and related circuitry for facilitating data communication through bus lines.
2. Description of Background Art
The use of bus signal lines is common in electronic system design. In processor-based systems, buses are used typically for reading and writing signals, for example, between a motherboard including a microprocessor and other system boards or nodes coupled to the bus, including memory devices, input/output controllers and other peripheral components.
Because bus signal lines are shared by various system components, bus arbitration means are provided typically to prevent contention between components desiring to access common signal lines simultaneously. Thus, according to some specified arbitration criteria, bus ownership may be granted to priority components requesting bus access.
To improve bus utilization, some bus arbiters allow so-called "split" transactions (i.e., instead of singular accessing events) to be performed during read or write operations. For example, a write operation might be split into two operations: data packet writing and then confirmation of writing completion. Similarly, a read operation might be split into a read request step, followed eventually by a read response step (including the read data packet).
By using previously unused "down" times between two halves of split transactions to perform other transactions, bus bandwidth may be increased significantly. However, for a bus arbitration scheme using split transactions to function properly, it is necessary for each node in the system to be able to process transactions which occur between corresponding split transaction events. For example, a bus master node should be able to handle a packet write operation after issuing a read request, but before its corresponding read response packet is received.
Unfortunately, not all components or peripheral boards which might be coupled electrically to system mother boards through conventional bus interfaces are configured for split transaction processing. In these cases, there is a risk that such unconfigured nodes, when connected to a split-transaction type bus interface, might cause a bus "deadlock," during which the unconfigured node fails to process new transactions arising between corresponding split transaction events. Accordingly, there is a need to provide a more effective bus communication technique wherein bus deadlock is avoided during split transactions.